4 April, 2017
CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for two days of networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems
Come join us and Vijay Pandiyan, Engineering Manager, who will be discussing thermal challenges in system design.
Session Track: PCB Simulation
Topic: Thermal Challenges in a System Design Enablement World
Speaker: Vijay Pandiyan, Engineering Manager, Future Facilities, Inc
Time: Wednesday, April 12, 2:15pm - 2:55pm, Room 212
Session Description: With rapid increase in need for high power and multi core semiconductors packages and system designs converging leading to very compact placement of components, product design teams are constantly facing challenges to keep the system from reaching thermal runway during peak power operations. The current practice of running thermal simulation with limited number of power profiles is no longer adequate due to the transient nature of the problem. This demands a tighter integration of system and package level design tools. This paper will discuss how Future Facilities is building thermal simulations for electronics industry that can be used early and often throughout the product design cycle. Integration with Cadence PCB and IC packaging design data supporting system design enablement strategy will be discussed.
For more information about the event agenda, visit here.
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